The Arrhenius equation derives an acceleration factor from 55oC to 125oC of 939ġ0 hours accelerated by a factor of 939 is 9,390 hours ~ 1 year (8,760 hours) JEDEC NAND reliability specification JESD47H, states that a bake time of 10 hours at 125oC is equivalent to 1 year data retention at 55oC The Arrhenius equation describes the rate of reaction for a given temperature (T), and activation energy (Ea) and can be used to calculate the acceleration in charge de-trapping for the NAND flash cell.Įxample of Arrhenius Equation calculation in JEDEC NAND standard In addition, charge naturally de-traps within a NAND cell over time, which is the limiting factor in NAND data retention.ĭe-trapping of stored charge is accelerated by exposure to high temperature, and the temperature that the NAND flash is subjected to is a critical factor. Shallow traps start de-trapping immediately after the cell is programmed, causing the cell threshold to decrease from the level set through the NAND program algorithm, leading to a potential “bit flip”. Other traps are shallow and as they collect charge, inhibit normal programming of the cell. At this point, programming the NAND will result in program failures and the entire block must be marked “bad” by the SSD. Some of the traps are deep, and eventually accumulate to the point where the tunnel oxide becomes conductive without application of an input voltage, and the cell is no longer capable of storing charge. The repeated electron tunneling mechanism from writing and erasing NAND cells causes the buildup of charge traps in the tunnel oxide layer. To read a NAND cell, a voltage above Vt is applied to the top gate and the current flowing in the transistor sensed by a sense amplifier, which gives information about the amount of charge stored in the cell. To erase a cell, the substrate well is raised to a high voltage forcing the electrons back through the oxide layer from the floating gate into the substrate. This is the process of writing (or programming) the NAND cell. To prevent the transistor from conducting current, electrons are forced through the thin oxide layer by the application of high voltage applied to the top gate. When voltage above the cell threshold, (Vt), is applied to the top gate, the transistor is “turned on” and conducts a current. In the floating-gate transistor, an insulating oxide layer resides between the floating gate and the substrate. The floating-gate transistor is the building block of all flash technology. This article describes these effects and provides some direction on the operation of a NAND flash based data storage system when exposed to different temperatures. NAND endurance is also impacted since endurance has an inverse relationship to data retention, and the rate of wear-out of NAND cells is affected by temperature at the time of programming and erasing NAND. The higher the temperature that the NAND flash experiences, the greater the acceleration of charge de-trapping mechanisms that could lead to random data bit failures. The ability of NAND flash to store and retain data depends on the temperature which the NAND flash is subjected to during writing, and between the time the data is written to the time the data is read. The effects of temperature on the data retention and endurance of the SSD, however, is rarely specified or discussed. These SSD products are typically screen-tested for functionality across the temperature range prior to shipment. Many NAND flash based SSD products on the market today are touted as “Industrial Grade” or as supporting “Industrial Temperature” (typically -40˚C to 85˚C) operation.